The next generation of computers and communications systems will handle data rates of several gigabits per second. Many systems will employ processors and SERDES chipsets that exceed gigahertz clock frequencies. Traditional parallel bus topologies have exhausted bandwidth. As parallel buses become wider, the complexity and cost of wiring on PCB boards increase dramatically. The increasing deviation between data and clock lines is increasingly difficult to solve in parallel buses. The solution is a fast serial channel. The newer serial bus architecture has rapidly replaced the parallel bus architecture of high-speed digital systems. Engineers have been turning to using multiple gigabit serial interconnect protocols with embedded clocks to achieve the goal of simple cabling and more bandwidth per channel.